Google has now shipped four different TPU systems in a single year, and the newest two say a lot about where AI hardware is heading. On Monday the company announced the TPU 8tx, built with AMD to keep data encrypted even while a model is working on it, and the TPU 8i Max, which glues two inference chips into one package to feed AI agents with huge context windows.
“This is the first time we have introduced four TPU systems in a single year,” wrote Amin Vahdat, Google’s SVP and chief technologist for AI and infrastructure. Neither chip is new silicon, though. Both are clever repackagings of the eighth generation chips Google showed in April, and that turns out to be the interesting part.
The short version
- TPU 8tx uses TPU 8t silicon with AMD EPYC hosts for hardware level confidential computing
- Google claims up to 2x lower latency than TPU 8t with a near zero performance penalty for the encryption
- TPU 8i Max packs two TPU 8i chips together: double the compute, 768 MB of SRAM and 17.2 TB/s of memory bandwidth
- Both target AI agents, regulated industries and long context work
- Vahdat told Bloomberg the systems will be available in 2027. No prices yet
Four TPUs in one generation
Back in April, Google split its TPU line in two for the first time. The TPU 8t is built for training, and the TPU 8i is built for inference, meaning the work of actually answering requests. Monday’s launch adds two specialized variants on top of those. Here is how the eighth generation family now lines up.
| System | Built from | Main job | Network |
|---|---|---|---|
| TPU 8t | New chip (April) | Training giant models | 3D torus |
| TPU 8i | New chip (April) | Low latency inference | Boardfly |
| TPU 8tx | 8t silicon + AMD EPYC hosts | Confidential training, fine tuning and agents | Boardfly |
| TPU 8i Max | Two 8i chips in one package | Long context inference | Boardfly |
TPU 8tx: encryption that stays on while the model works
Most computers protect data in two states. Data sitting on a disk is encrypted at rest, and data moving across a network is encrypted in transit. But the moment a processor actually works on that data, it normally has to be decrypted in memory. That third state, data in use, is the weak spot. A compromised host, a rogue admin or a cloud provider with too much access could in theory read it.
Confidential computing closes that gap by running workloads inside a hardware isolated trusted execution environment, where memory stays encrypted and the host system cannot peek in. CPUs have offered this for years. The hard part has been extending it to the AI accelerators where the heavy lifting happens.
Google’s answer pairs the TPU 8t silicon with custom 5th Gen AMD EPYC “Turin” processors as hosts. AMD’s Secure Encrypted Virtualization, or SEV, already protects memory on the CPU side, and in the 8tx that protection extends across the link to the connected TPUs. ServeTheHome reports that a dual socket Turin setup supplies 128 PCIe Gen5 lanes, enough to feed four TPUs and fast network cards without any I/O bottleneck.
Google says the chip “builds security directly into the hardware layer, keeping sensitive data and model weights protected and isolated even while in active use.” The pitch is aimed squarely at “regulated enterprises and governments running frontier or proprietary models and autonomous agents alongside their most sensitive data.”
Why it borrows the inference network
Even though the 8tx is based on the training chip, it uses Boardfly, the network topology from the inference focused TPU 8i, instead of the 8t’s 3D torus. Boardfly connects chips so that any two are at most seven hops apart, compared with sixteen in the torus design. Fewer hops means faster responses, which matters a lot for agents that fire off long chains of sequential model calls.
That is also where the “2x lower latency” claim comes from. The 8tx has a custom inference network that lets it run reasoning alongside training, so a company can distill and train small models on the fly using proprietary data that never leaves the protected environment.
TPU 8i Max: two chips, one package
The second launch tackles a different problem. When an agent reads an entire codebase or hours of video, the bottleneck is usually not raw compute. It is memory: how much the chip can hold close by and how fast it can move it. Engineers call this the memory wall.
Google’s fix is blunt but effective. The TPU 8i Max fuses two TPU 8i chips into a single multi chip package, which Vahdat says delivers “double the compute, double the SRAM and double the HBM bandwidth of TPU 8i” while fitting “twice the silicon within the existing rack footprint.”
| Spec | TPU 8t | TPU 8i | TPU 8i Max |
|---|---|---|---|
| HBM capacity | 216 GB | 288 GB | 384 GB* |
| HBM bandwidth | about 6.5 TB/s | 8.6 TB/s | 17.2 TB/s |
| On-chip SRAM | 128 MB | 384 MB | 768 MB |
| Peak FP4 compute | 12.6 PFLOPS | 10.1 PFLOPS | About 2x TPU 8i |
| Best for | Training | Fast answers | Huge context windows |
*As reported by ServeTheHome, which describes it as about a third more than TPU 8i. Google has emphasized the doubled bandwidth and SRAM rather than capacity.
The SRAM number is the one to watch. SRAM is the tiny, ultra fast memory that sits right on the chip, and having 768 MB of it means more of a model’s working state, like the key value cache that grows with every token of context, can stay close to the compute instead of making slow trips out to HBM. Google told ServeTheHome that customers who need data to stay inside the confidential domain should still use the 8tx for serving, since the 8i Max does not carry the same protections.
Why Google keeps remixing chips
The bigger story is speed of iteration. Designing a new chip takes years. Repackaging existing silicon with a new host, a new network or a second die takes months. AI Weekly summed it up neatly: Google’s release pace is “a system integration advantage, not a fabrication one.”
That matters because the AI market changes faster than chip roadmaps. A year ago, few customers were asking for encrypted training or million token context windows. Now regulated banks and governments want both. Being able to answer with a variant instead of a new tapeout is a real edge.
Google is also working on the software side, which has long been the main reason teams stick with Nvidia. Alongside the chips it open sourced TorchTPU for running PyTorch natively on TPUs, shipped a TPU Agent Suite, launched the XLA Serving Engine and made Cloud Pathways generally available on Google Kubernetes Engine. Google says the full eighth generation lineup offers up to 2.7x better training performance and 80% better inference price performance than the previous generation.
The Nvidia question
Every hyperscaler is trying to depend less on Nvidia. Amazon has Trainium, Microsoft has Maia, and the AI labs themselves want in, with reports that Anthropic is building its own AI chip. Google is the furthest along of the big clouds, with TPUs now serving close to 100 customers across frontier labs, trading firms, retailers and universities, according to Vahdat.
The timing is awkward for Nvidia. The launch landed days after CEO Jensen Huang admitted to an affair with a woman alleged to be a Chinese intelligence asset, and Nvidia is now investigating whether it was a spy operation. A chip built around keeping data and model weights locked down, even from the people running the hardware, is a pointed thing to launch that week, whether Google intended it or not.
There is also a quiet winner here: AMD. Landing EPYC as the host CPU in a non AMD accelerator system at a major hyperscaler, and doing it on the strength of its confidential computing features, is a credibility boost even if it will not swing server market share overnight.
Read the claims carefully
- Google has not published independent benchmarks for either system
- “Double the hardware” does not mean double the speed for every app. Workloads limited by networking or storage may see less
- The “near zero” encryption penalty is a vendor claim that needs third party testing
- There is no pricing, no list of cloud regions and no firm ship date beyond 2027
What to watch next
- Pricing for TPU 8tx and 8i Max when Google Cloud opens them up in 2027
- The first named 8tx customer from government or banking, which would prove the confidential computing pitch
- Whether Google publishes the attestation chain that ties the TPU to the AMD host enclave, so outsiders can audit it
- Head to head long context tests against Nvidia’s Blackwell and Rubin systems
The takeaway is simple. The AI chip race is no longer only about who has the fastest processor. It is about who can hand a bank a box that keeps its data secret, or hand an agent a chip that can hold an entire codebase in memory, and do it before the market moves on again. With four TPU systems in a year, Google is making the case that it can.
Sources and further reading
- TechCrunch: Google broadens its AI hardware portfolio with two new specialized chips
- AI Weekly: Google unveils TPU 8tx and 8i Max for secure, long-context AI
- ServeTheHome: Google TPU 8tx and TPU 8i Max
- AMD Newsroom: AMD EPYC and Google TPU 8tx
Featured image: close-up of a computer processor, free stock photo via Pexels.
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